This invention relates to a semiconductor memory circuit, and particularly to a semiconductor memory circuit which features a method of controlling a data bus employed in a dynamic random access memory (hereinafter "DRAM").
As this type of circuit, there has heretofore been known one disclosed in Japanese Laid-Open Patent Application No. 207088/1991.
FIG. 4 is a block diagram schematically showing the structure of a read unit employed in the DRAM. The configuration shown in FIG. 4 is a general DRAM's memory cell block diagram. The present invention has also such configuration.
In FIG. 4, external address signals supplied from the outside are converted into internal address signals by an address buffer AB. Next, the converted internal address signals are input to an X decoder ADX and a Y decoder ADY respectively. The contents stored at a predetermined address in a memory cell array MA, which has been selected by the X decoder ADX and the Y decoder ADY, are output to an output buffer OB through a sense amplifier (SA) and an input/output interface circuit (I/O) SI. Thereafter, the contents are read out as output data Dout from the output buffer OB. The entire operation of the read unit is controlled based on various control signals VB, Rn, oE, oP and oS output from a control signal generating circuit CG.
However, in the aforementioned conventional semiconductor memory circuit, if excessive allowance for the timing for electrically connecting the bit line pair to the data buses is made, then a quick access cannot be obtained. Further, when the data buses are electrically connected to the bit line pair before a sufficient sense operation is performed, information stored in each of the cells arranged within a memory cell array is destroyed due to variations in process and the like.